1 ? fn6683.2 ISL97519A 600khz/1.2mhz pwm step-up regulator the ISL97519A is a high frequency, high efficiency step-up voltage regulator operated at constant frequency pwm mode. with an internal 2.0a, 200m mosfet, it can deliver up to 1a output current at over 90% efficiency. two selectable frequencies, 600khz and 1.2mhz, allow trade offs between smaller components and faster transient response. an external compensation pin gives the user greater flexibility in setting frequency compensation allowing the use of low esr ceramic output capacitors. when shut down, it draws <1a of current and can operate down to 2.3v input supply. these features along with 1.2mhz switching frequency makes it an ideal device for portable equipment and tft-lcd displays. the ISL97519A is available in an 8 ld msop package with a maximum height of 1.1mm. the device is specified for operation over the full -40c to +85c temperature range. pinout ISL97519A (8 ld msop) top view features ? >90% efficiency ? 2.0a, 200m power mosfet ? 2.3v to 5.5v input ? up to 25v output ? 600khz/1.2mhz switchi ng frequency selection ? adjustable soft-start ? internal thermal protection ? 1.1mm max height 8 ld msop package ? pb-free (rohs compliant) ? halogen free applications ? tft-lcd displays ? dsl modems ? pcmcia cards ? digital cameras ? gsm/cdma phones ? portable equipment ? handheld devices fb fsel en vdd gnd lx comp ss 1 2 3 4 8 7 6 5 ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL97519Aiuz 7519a 8 ld msop mdp0043 ISL97519Aiuz-t* 7519a 8 ld msop mdp0043 ISL97519Aiuz-tk* 7519a 8 ld msop mdp0043 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet june 30, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6683.2 june 30, 2008 absolute maxi mum ratings (t a = +25c) thermal information lx to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27v v dd to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6v comp, fb, en, ss, fsel to gnd . . . . . . . . . -0.3v to (v dd +0.3v) storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +135c power dissipation . . . . . . . . . . . . . . . . . . . . . see curves on page 5 pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v in = 3.3v, v out = 12v, i out = 0ma, fsel = gnd, t a = -40c to +85c unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. parameter description conditions min typ max unit iq1 quiescent current - shutdown en = 0v 1 5 a iq2 quiescent current - not switching en = v dd , fb = 1.3v 0.7 ma iq3 quiescent current - switching en = v dd , fb = 1.0v 3 4.5 ma v fb feedback voltage 1.228 1.24 1.252 v i b-fb feedback input bias current 0.01 0.5 a v dd input voltage range 2.3 5.5 v d max -600khz maximum duty cycle fsel = 0v 85 92 % d max -1.2mhz maximum duty cycle fsel = v dd 85 90 % i lim1 current limit - max peak input current v dd < 2.8v 1.0 a i lim2 current limit - max peak input current v dd > 2.8v 1.5 2.0 a i en shutdown input bias current en = 0v 0.01 0.5 a r ds(on) switch on-resistance v dd = 2.7v, i lx = 1a 0.2 i lx-leak switch leakage current vsw = 27v 0.01 3 a v out / v in line regulation 3v < v in < 5.5v, v out = 12v 0.2 % v out / i out load regulation v in = 3.3v, v out = 12v, i o = 30ma to 200ma 0.3 % f osc1 switching frequency accuracy fsel = 0v 500 620 740 khz f osc2 switching frequency accuracy fsel = v dd 1000 1250 1500 khz v il en, fsel input low level 0.5 v v ih en, fsel input high level 1.5 v g m error amp tranconductance i = 5a 70 130 150 1/ v dd-on v dd uvlo on threshold 1.95 2.1 2.25 v hys v dd uvlo hysteresis 140 mv i ss soft-start charge current 2 3 4 a v ss -en minimum soft-start enable voltage 40 65 150 mv ilim-v ss -en current limit around ss enable v ss = 200mv 300 350 400 ma otp over-temperature protection 150 c ISL97519A
3 fn6683.2 june 30, 2008 block diagram typical application circuit comparator oscillator shutdown and start-up control lx vdd fsel en ss reference generator pwm logic controller fet driver current sense gm amplifier gnd fb comp pin descriptions pin number pin name description 1 comp compensation pin. output of the internal error ampl ifier. capacitor and resistor from comp pin to ground. 2 fb voltage feedback pin. internal reference is 1. 24v nominal. connect a resistor divider from v out . v out = 1.24v (1 + r 1 /r 2 ). see ?typical application circuit? on page 3. 3 en shutdown control pin. pull en low to turn off the device. 4 gnd analog and power ground. 5 lx power switch pin. connected to the drain of the internal power mosfet. 6 vdd analog power supply input pin. 7 fsel frequency select pin. when fsel is set low, sw itching frequency is set to 620khz. when connected to high or vdd, switching frequency is set to 1.25mhz. 8 ss soft-start control pin. connect a capacitor to control the converter start-up. 1 2 3 4 8 7 6 5 comp fb en gnd ss fsel vdd lx + + 1k 4.7nf 27nf 22f c 4 c 1 0.1f 10h d 1 22f c 3 12v 2.3v to 5.5v r 3 c 5 85.2k r 1 10k r 2 c 2 s1 c 5 open ISL97519A
4 fn6683.2 june 30, 2008 typical performance curves figure 1. boost efficiency vs i out figure 2. boost efficiency vs i out figure 3. load regulation vs i out figure 4. load regulation vs i out figure 5. line regulation vs v in figure 6. transient response 60 65 70 75 80 85 90 95 0 200 400 600 800 1000 i out (ma) efficiency (%) v in = 5v, v o = 12v, f s = 620 khz v in = 5v, v o = 12v, f s = 1.25 mhz v in = 5v, v o = 9v, f s = 620 khz v in = 5v, v o = 9v, f s = 1.25mhz 74 76 78 80 82 84 86 88 90 92 0 100 200 300 400 500 i out (ma) efficiency (%) v in = 3.3v, v o = 12v, v in = 3.3v, v o = 9v, v in = 3.3v, v o = 9v, v in = 3.3v, v o = 12v, f s = 1.25mhz f s = 1.25mhz f s = 620khz f s = 620khz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 200 400 600 800 1000 i out (ma) load regulation (%) v in = 5v, v o = 12v, f s = 1.25mhz v in = 5v, v o = 12v, f s = 620khz v in = 5v, v o = 9v, f s = 620khz v in = 5v, v o = 9v, f s = 1.25mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 100 200 300 400 500 i out (ma) load regulation (%) v in = 3.3v, v o = 12v, f s = 1.25mhz v in = 3.3, v o = 12v, f s = 620khz v in = 3.3v, v o = 9v, f s = 1.25mhz v in = 3.3, v o = 9v, f s = 620khz -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 2 v in (v) line regulation (%) 3 4 5 6 v o = 12v, i o = 80ma f s = 1.25mhz v o = 12v, i o = 80ma f s = 620khz v o = 9v, i o = 80ma f s = 1.25mhz v o = 9v, i o = 100ma f s = 620khz v o = 12v f s = 600khz v in = 3.3v i o = 50ma to 300ma ISL97519A
5 fn6683.2 june 30, 2008 applications information the ISL97519A is a high frequency, high efficiency boost regulator operated at constant frequency pwm mode. the boost converter stores energy from an input voltage source and delivers it to a higher output voltage. the input voltage range is 2.3v to 5.5v and output voltage range is 5v to 25v. the switching frequency is selectable between 600khz and 1.2mhz allowing smaller indu ctors and faster transient response. an external compensation pin gives the user greater flexibility in setting output transient response and tighter load regulation. the conv erter soft-start characteristic can also be controlled by external c ss capacitor. the en pin allows the user to completely shutdown the device. boost converter operations figure 11 shows a boost converter with all the key components. in steady state operating and continuous conduction mode where the inductor current is continuous, the boost converter operates in two cycles. duri ng the first cycle, as shown in figure 12, the internal power fet turns on and the schottky diode is reverse biased and cuts off the current flow to the output. the output current is supplied from the output capacitor. the voltage across the inductor is v in and the inductor current ramps up in a rate of v in /l, l is the inductance. the inductance is magnetized and energy is stored in the inductor. the change in inductor current is shown in equation 1: figure 7. transient response figure 8. ss delay and lx delay during en = vdd start- up figure 9. package power dissipation vs ambient temperature figure 10. package power dissipation vs ambient temperature typical performance curves (continued) v o = 12v f s = 1.2mhz v in = 3.3v i o = 50ma to 300ma jedec jesd51-7 high effective thermal conductivity test board 1.0 0.9 0.6 0.4 0.3 0.2 0.1 0 0 255075100125 ambient temperature (c) power dissipation (w) 85 870mw j a = + 1 1 5 c / w m s o p 8 0.8 0.5 0.7 jedec jesd51-3 low effective thermal conductivity test board 0.6 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 486mw j a = + 2 0 6 c / w m s o p 8 0.5 i l1 t1 v in l --------- = t1 d f sw ------------ = d duty cycle = v o i out c out --------------- - t 1 = (eq. 1) ISL97519A
6 fn6683.2 june 30, 2008 during the second cycle, the power fet turns off and the schottky diode is forward biased, (see figure 13). the energy stored in the inductor is pumped to the output supplying output current and charging the output capacitor. the schottky diode side of the inductor is clamped to a schottky diode above the output voltage. so the voltage drop across the inductor is v in - v out . the change in inductor current during the second cycle is shown in equation 2: for stable operation, the same amount of energy stored in the inductor must be taken out. the change in inductor current during the two cycles mu st be the same as shown in equation 3. output voltage an external feedback resistor divider is required to divide the output voltage down to the nominal 1.24v reference voltage. the current drawn by the resi stor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network less than 100k is recommended. the boost converter output voltage is determined by the relationship in equation 4: the nominal vfb voltage is 1.24v. inductor selection the inductor selection determines the output ripple voltage, transient response, output current capability, and efficiency. its selection depends on the inpu t voltage, output voltage, switching frequency, and maximum output current. for most applications, the inductance should be in the range of 2h to 33h. the inductor maximum dc current specification must be greater than the peak inductor current required by the regulator.the peak inductor current can be calculated in equation 5: output capacitor low esr capacitors should be used to minimized the output voltage ripple. multi-layer cera mic capacitors (x5r and x7r) are preferred for the output capacitors because of their lower esr and small packages. tantalum capacitors with higher esr can also be used. the output ripple can be calculated as shown in equation 6: for noise sensitive application, a 0.1f placed in parallel with the larger output capacitor is recommended to reduce the switching noise coupled from the lx switching node. i l t2 v in v out ? l ------------------------------- - = t2 1d ? f sw ------------- = (eq. 2) i1 i2 + 0 = d f sw ------------ v in l --------- 1d ? f sw ------------- v in v out ? l ------------------------------- - + 0 = v out v in --------------- - 1 1d ? ------------- = (eq. 3) ISL97519A c out c in ld v in v out c out c in ld v in v out figure 11. boost converter c out c in l v in v out t 1 v o i l i l1 ISL97519A figure 12. boost converter - cycle 1, power switch close ISL97519A c out c in ld v in v out t 2 v o i l2 i l figure 13. boost converter - cycle 2, power switch open v out v fb 1 r 1 r 2 ------ - + ?? ?? ?? = (eq. 4) i l peak () i out v out v in ----------------------------------- - 12 ? v in v out v in ? () lv out freq ---------------------------------------------------- - + = (eq. 5) v o i out d f sw c o --------------------------- i out esr + = (eq. 6) ISL97519A
7 fn6683.2 june 30, 2008 schottky diode in selecting the schottky di ode, the reverse break down voltage, forward current and forward voltage drop must be considered for optimum conver ter performance. the diode must be rated to handle 2.0a, the current limit of the ISL97519A. the breakdown voltage must exceed the maximum output voltage. low forward voltage drop, low leakage current, and fast reverse recovery will help the converter to achieve the maximum efficiency. input capacitor the value of the input capacitor depends the input and output voltages, the maximum ou tput current, the inductor value and the noise allowed to put back on the input line. for most applications, a minimu m 10f is required. for applications that run close to the maximum output current limit, input capacitor in the range of 22f to 47f is recommended. the ISL97519A is powered from the vin. a high frequency 0.1f bypass capacitor is recommended to be close to the vin pin to reduce supply line noise and ensure stable operation. loop compensation the ISL97519A incorporates a transconductance amplifier in its feedback path to allow the user some adjustment on the transient response and better regulation. the ISL97519A uses current mode control arch itecture which has a fast current sense loop and a slow voltage feedback loop. the fast current feedback loop does not require any compensation. the slow voltage loop must be compensated for stable operation. the compensation network is a series rc network from comp pin to gr ound. the resistor sets the high frequency integrator gain for fast transient response and the capacitor sets the integrator zero to ensure loop stability. for most applications, the compensation resistor in the range of 0.5k to 7.5k and the compensation capacitor in the range of 3nf to 10nf. soft-start during power-up, assuming en is tied to vdd, as vdd rises above vdd uvlo, the ss capacitor begins to charge up with a constant 3a current. during the time the part takes to rise to 60mv the boost will not be enabled. depending on the value of the capacitor on the ss pin, this provides sufficient (540s for a 27nf capacitor or 2ms for a 100nf capacitor) time for the passive in-rush current to settle down, allowing the output capacitors to be charged to a diode drop below vdd. after the ss pin passes above the threshold beyond which the part is enabled (60mv) the part begins to switch. the linearly rising ss voltage, at a charge rate proportional to 3a, has a direct effect on t he current limit allowing the current limit to linearly ramp -up to full current limit. ss voltage of 200mv corresponds to a current limit around 350ma and 0.6v corresponds to full current limit. the total soft-start time is calculated in equation 7: the full current is available after the soft-start period is finished. the soft-start capacitor should be selected to be big enough that it doesn't reach 0.6v before the output voltage reaches the final value. when the ISL97519A is disabled, the soft-start capacitor will be discharged to ground. frequency selection the ISL97519A switching frequency can be user selected to operate at either constant 62 0khz or 1.25mhz. connecting f sel pin to ground sets the pwm switching frequency to 620khz. when connecting f sel high or v dd , the switching frequency is set to 1.25mhz. shutdown control when the en pin is pulled down, the ISL97519A is shutdown reducing the supply current to <1a. maximum output current the mosfet current limit is nominally 2.0a and guaranteed 1.5a when v dd is greater than 2.8v. this restricts the maximum output current, i omax , based on equation 8: where: i l = mosfet current limit i l-avg = average inductor current i l = inductor ripple current v diode = schottky diode forward voltage, typically, 0.6v f s = switching frequency, 600khz or 1.2mhz d = mosfet turn-on ratio: table 1 gives typical maximum i out values for 1.2mhz switching frequency and 10h inductor. t ss css 0.6v 3 a ----------------------------- - css 2 10 5 == (eq. 7) i l i l-avg 12 ? i l () + = (eq. 8) i l v in v o v diode + () v in ? [] lv o ( v diode ) f s + ------------------------------------------------------------------------------ = (eq. 9) i l-avg i out 1d ? ------------- = (eq. 10) d1 v in v out v diode + -------------------------------------------- ? = (eq. 11) ISL97519A
8 fn6683.2 june 30, 2008 cascaded mosfet application a 25v n-channel mosfet is integrated in the boost regulator. for applications where the output voltage is greater than 25v, an external cascaded mosfet is needed as shown in figure 14. the voltage rating of the external mosfet should be greater than a vdd . dc path block application note that there is a dc path in the boost converter from the input to the output through the inductor and diode. the input voltage will be seen at the output less a forward voltage drop of the diode before the part is enabled. if this direct connection is not desired, the following circuit can be inserted between input and inductor to disconnect the dc path when the part is disabled (see figure 15). table 1. typical maximum i out values v in (v) v out (v) i omax (ma) 3.3 5 1150 3.3 9 655 3.3 12 500 5 9 990 5 12 750 figure 14. cascaded mosfet topology for high output voltage applications intersil ISL97519A lx fb a vdd v in figure 15. circuit to disconnect the dc path of boost converter input en to inductor ISL97519A
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6683.2 june 30, 2008 ISL97519A mini so package family (msop) 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3?e gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 mdp0043 mini so package family symbol millimeters tolerance notes msop8 msop10 a1.101.10 max. - a1 0.10 0.10 0.05 - a2 0.86 0.86 0.09 - b 0.33 0.23 +0.07/-0.08 - c0.180.18 0.05 - d 3.00 3.00 0.10 1, 3 e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. d 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
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